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| kinetis k66 sub-family 180 mhz arm? cortex?-m4f microcontroller. the k66 sub-family members provide greater performance, memory options up to 2 mb total flash and 256 kb of sram, as well as higher peripheral integration with features such as dual usb and a 10/100 mbit/s ethernet mac. these devices maintain hardware and software compatibility with the existing kinetis family. this product also offers: ? integration of a high speed usb physical transceiver ? greater performance flexibility with a high speed run mode ? smarter peripherals with operation in stop modes performance ? up to 180 mhz arm cortex-m4 based core with dsp instructions and single precision floating point unit system and clocks ? multiple low-power modes to provide power optimization based on application requirements ? memory protection unit with multi-master protection ? 3 to 32 mhz main crystal oscillator ? 32 khz low power crystal oscillator ? 48 mhz internal reference security ? hardware random-number generator ? supports des, aes, sha accelerator (cau) ? multiple levels of embedded flash security timers ? four periodic interrupt timers ? 16-bit low-power timer ? two 16-bit low-power timer pwm modules ? two 8-channel motor control/general purpose/pwm timers ? two 2-ch quad decoder/general purpose timers ? real-time clock human-machine interface ? low-power hardware touch sensor interface (tsi) ? general-purpose input/output memories and memory expansion ? up to 2 mb program flash memory on non- flexmemory devices with 256 kb ram ? up to 1 mb program flash memory and 256 kb of flexnvm on flexmemory devices ? 4 kb flexram on flexmemory devices ? flexbus external bus interface and sdram controller analog modules ? two 16-bit sar adcs and two 12-bit dac ? four analog comparators (cmp) containing a 6-bit dac and programmable reference input ? voltage reference 1.2v communication interfaces ? ethernet controller with mii and rmii interface to external phy and hardware ieee 1588 capability ? usb high-/full-/low-speed on-the-go with on-chip high speed transceiver ? usb full-/low-speed otg with on-chip transceiver ? two can, three spi and four i2c modules ? low power universal asynchronous receiver/ transmitter 0 (lpuart0) and five standard uarts ? secure digital host controller (sdhc) ? i2s module operating characteristics ? voltage/flash write voltage range:1.71 to 3.6 v ? temperature range (ambient): -40 to 105c mk66fn2m0vmd18 mk66fx1m0vmd18 mk66fn2m0vlq18 mk66fx1m0vlq18 144 mapbga (md) 13 mm x 13 mm pitch 1 mm 144 lqfp (lq) 20 mm x 20 mm pitch 0.5 mm nxp semiconductors K66P144M180SF5V2 data sheet: technical data rev. 4, 04/2017 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
ordering information 1 part number memory maximum number of i\o's flash sram mk66fn2m0vmd18 2 mb 256 kb 100 mk66fx1m0vmd18 1.25 mb 256 kb 100 mk66fn2m0vlq18 2 mb 256 kb 100 mk66fx1m0vlq18 1.25 mb 256 kb 100 1. to confirm current availability of orderable part numbers, go to http://www.nxp.com and perform a part number search. related resources type description resource selector guide the nxp solution advisor is a web-based tool that features interactive application wizards and a dynamic product selector. solution advisor reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. k66p144m180sf5rmv2 1 data sheet the data sheet includes electrical characteristics and signal connections. this document. chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. kinetis_k_0n65n 1 package drawing package dimensions are provided in package drawings. ? mapbga 144-pin : 98asa00222d 1 ? lqfp 144-pin: 98ass23177w 1 1. to find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors memories and memory interfaces program flash ram 12-bit dac x2 6-bit dac x4 crc interface touch-sensing programmable analog timers communication interfaces security and integrity spi x3 carrier modulator transmitter flexmemory clocks frequency- core debug interfaces dsp interrupt controller comparator x4 analog voltage reference secure digital low power timer human-machine interface (hmi) gpio system protection memory dma internal watchdogs and external low-leakage wakeup locked loop serial programming interface phase- locked loop reference internal clocks delay block timers interrupt periodic external bus real-time independent clock oscillators low/high frequency uart x5 xtrinsic ? cortex -m4 arm low power tpm x 2 (4ch) lpuart sdram ? kinetis k66 sub-family usb dcd/ usbhsdcd usb voltage regulator usb ls/fs otg controller with transceiver usb ls/fs/hs otg controller with transceiver x1 i s 2 floating- point unit controller x4 i c 2 timers x4 (20ch) can x2 ieee 1588 timers ethernet ieee 1588 hardware encryption number random generator cache 16-bit adc x2 figure 1. k66 block diagram kinetis k66 sub-family, rev. 4, 04/2017 3 nxp semiconductors table of contents 1 ratings.................................................................................... 5 1.1 thermal handling ratings................................................. 5 1.2 moisture handling ratings................................................ 5 1.3 esd handling ratings....................................................... 5 1.4 voltage and current operating ratings............................. 5 2 general................................................................................... 6 2.1 ac electrical characteristics............................................. 6 2.2 nonswitching electrical specifications.............................. 7 2.2.1 voltage and current operating requirements..... 7 2.2.2 lvd and por operating requirements............. 8 2.2.3 voltage and current operating behaviors.......... 9 2.2.4 power mode transition operating behaviors...... 10 2.2.5 power consumption operating behaviors.......... 12 2.2.6 emc radiated emissions operating behaviors... 16 2.2.7 designing with radiated emissions in mind....... 17 2.2.8 capacitance attributes...................................... 17 2.3 switching specifications................................................... 17 2.3.1 device clock specifications............................... 17 2.3.2 general switching specifications....................... 18 2.4 thermal specifications..................................................... 19 2.4.1 thermal operating requirements....................... 19 2.4.2 thermal attributes............................................. 19 3 peripheral operating requirements and behaviors.................. 21 3.1 core modules.................................................................. 21 3.1.1 debug trace timing specifications..................... 21 3.1.2 jtag electricals................................................ 21 3.2 system modules.............................................................. 24 3.3 clock modules................................................................. 24 3.3.1 mcg specifications........................................... 24 3.3.2 irc48m specifications...................................... 27 3.3.3 oscillator electrical specifications..................... 28 3.3.4 32 khz oscillator electrical characteristics......... 31 3.4 memories and memory interfaces................................... 31 3.4.1 flash (ftfe) electrical specifications............... 31 3.4.2 ezport switching specifications......................... 36 3.4.3 flexbus switching specifications....................... 37 3.4.4 sdram controller specifications....................... 40 3.5 security and integrity modules........................................ 43 3.6 analog............................................................................. 43 3.6.1 adc electrical specifications............................. 43 3.6.2 cmp and 6-bit dac electrical specifications..... 48 3.6.3 12-bit dac electrical characteristics................. 50 3.6.4 voltage reference electrical specifications........ 53 3.7 timers.............................................................................. 54 3.8 communication interfaces............................................... 54 3.8.1 ethernet switching specifications...................... 55 3.8.2 usb voltage regulator electrical specifications.................................................... 58 3.8.3 usb full speed transceiver and high speed phy specifications............................................ 59 3.8.4 usb dcd electrical specifications.................... 60 3.8.5 can switching specifications............................ 60 3.8.6 dspi switching specifications (limited voltage range)................................................................ 60 3.8.7 dspi switching specifications (full voltage range)................................................................ 62 3.8.8 inter-integrated circuit interface (i2c) timing.... 64 3.8.9 uart switching specifications.......................... 65 3.8.10 low power uart switching specifications....... 65 3.8.11 sdhc specifications......................................... 66 3.8.12 i2s switching specifications.............................. 67 3.9 human-machine interfaces (hmi).................................... 73 3.9.1 tsi electrical specifications............................... 73 4 dimensions............................................................................. 73 4.1 obtaining package dimensions....................................... 73 5 pinout...................................................................................... 74 5.1 k66 signal multiplexing and pin assignments................. 74 5.2 recommended connection for unused analog and digital pins........................................................................ 81 5.3 k66 pinouts..................................................................... 82 6 ordering parts......................................................................... 84 6.1 determining valid orderable parts.................................... 84 7 part identification..................................................................... 85 7.1 description....................................................................... 85 7.2 format............................................................................. 85 7.3 fields............................................................................... 85 7.4 example........................................................................... 86 8 terminology and guidelines.................................................... 86 8.1 definitions........................................................................ 86 8.2 examples......................................................................... 87 8.3 typical-value conditions.................................................. 87 8.4 relationship between ratings and operating requirements.................................................................... 88 8.5 guidelines for ratings and operating requirements.......... 88 9 revision history...................................................................... 89 4 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 1 ratings 1.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model -2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model -500 +500 v 2 i lat latch-up current at ambient temperature of 105c -100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78, ic latch-up test . 1.4 voltage and current operating ratings ratings kinetis k66 sub-family, rev. 4, 04/2017 5 nxp semiconductors symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 300 ma v dio digital 1 input voltage,including reset_b C0.3 v dd + 0.3 v v aio analog 1 input voltage, including extal32 and xtal32 C0.3 v dd + 0.3 v i d maximum current single pin limit (digital output pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v v usb0_dp usb0_dp input voltage C0.3 3.63 v v usb1_dp usb1_dp input voltage C0.3 3.63 v v usb0_dm usb0_dm input voltage C0.3 3.63 v v usb1_dm usb1_dm input voltage C0.3 3.63 v v usb1_vbus usb1_vbus detect voltage C0.3 6.0 v vreg_in0, vreg_in1 usb regulator input C0.3 6.0 v v bat rtc battery supply voltage C0.3 3.8 v 1. digital pins have a general purpose i/o port assigned (e.g. pta0). analog pins do not have an associated general purpose i/o port. 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 2. input signal measurement reference all digital i/o switching characteristics assume: 1. output pins general 6 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors ? have c l =30pf loads, ? are slew rate disabled, and ? are normal drive strength 2. input pins ? have their passive filter disabled (portx_pcrn[pfe]=0) 2.2 nonswitching electrical specifications 2.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.71 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.71 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icdio digital 1 input pin negative dc injection current (except rtc_wakeup pins) single pin ? v in < v ss -0.3v -5 ma 2 i icaio analog 1 input pin dc injection current single pin ? v in < v ss -0.3v (negative current injection) -5 ma 2 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents of 16 contiguous pin ? negative current injection -25 ma v odpu pseudo open drain pullup voltage level v dd v dd v 3 v ram v dd voltage required to retain ram 1.2 v v rfvbat v bat voltage required to retain the vbat register file v por_vbat v general kinetis k66 sub-family, rev. 4, 04/2017 7 nxp semiconductors 1. digital pins have a general purpose i/o port assigned (e.g. pta0). analog pins do not have an associated general purpose i/o port. 2. all digital and analog i/o pins are internally clamped to v ss through an esd protection diode. there is no diode connection to v dd . if v in is less than vss-0.3v, a current limiting resistor is required. the minimum negative dc injection current limiting resistor value is calculated as r=(-0.3-v in )/|i icdio | or r=(-0.3-v in )/|i icaio |. the actual resistor should be an order of magnitude higher to tolerate transient voltages. 3. open drain outputs must be pulled to vdd. 2.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 80 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 60 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising threshold is the sum of falling threshold and hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v general 8 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 2.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. typ. max. unit notes v oh output high voltage normal drive pad ? 2.7 v v dd 3.6 v, i oh = -10ma ? 1.71 v v dd 2.7 v, i oh = -5ma v dd C 0.5 v dd C 0.5 v v output high voltage high drive pad ? 2.7 v v dd 3.6 v, i oh = -20ma ? 1.71 v v dd 2.7 v, i oh = -10ma v dd C 0.5 v dd C 0.5 v v i oht output high current total for all ports 100 ma v oh_rtc_wakeup output high voltage normal drive pad ? 2.7 v v bat 3.6 v, i oh = -5 ma ? 1.71 v v bat 2.7 v, i oh = -2.5 ma v bat C 0.5 v bat C 0.5 v v i oh_rtc_wakeup output high current total for rtc_wakeup pins 100 ma v ol output low voltage normal drive pad ? 2.7 v v dd 3.6 v, i ol = 10 ma ? 1.71 v v dd 2.7 v, i ol = 5 ma 0.5 0.5 v v output low voltage high drive pad ? 2.7 v v dd 3.6 v, i ol = 20 ma ? 1.71 v v dd 2.7 v, i ol = 10 ma 0.5 0.5 v v i olt output low current total for all ports 100 ma v ol_rtc_wakeup output low voltage normal drive pad ? 2.7 v v bat 3.6 v, i ol = 5 ma ? 1.71 v v bat 2.7 v, i ol = 2.5ma 0.5 0.5 v v i ol_rtc_wakeup output low current total for rtc_wakeuppins 100 ma i in input leakage current, analog and digital pins ? v ss v in v dd 0.002 0.5 a 1 i oz_rtc_wakeup hi-z (off-state) leakage current (per rtc_wakeup pin) 0.25 a r pu internal pullup resistors 20 50 k? 2 r pd internal pulldown resistors 20 50 k? 3 1. measured at vdd=3.6v 2. measured at v dd supply voltage = v dd min and vinput = v ss general kinetis k66 sub-family, rev. 4, 04/2017 9 nxp semiconductors 3. measured at v dd supply voltage = v dd min and vinput = v dd 2.2.4 power mode transition operating behaviors all specifications except t por , and vllsx C> run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 100mhz ? bus clock = 50mhz ? flexbus clock = 50 mhz ? flash clock = 25 mhz ? mcg mode=fei table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. 300 s ? vlls0 C> run 172 s ? vlls1 C> run 172 s ? vlls2 C> run 94 s ? vlls3 C> run 94 s ? lls2 C> run 5.8 s ? lls3 C> run 5.8 s ? vlps C> run 5.4 s ? stop C> run 5.4 s table 6. low power mode peripheral adders typical value symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 56 a table continues on the next page... general 10 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors table 6. low power mode peripheral adders typical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 i irefsten32kh z 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 52 a i erefsten4mh z external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 228 237 245 251 258 ua i erefsten32k hz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. vlls1 vlls3 lls2 lls3 vlps stop 440 440 490 490 510 510 490 490 490 490 560 560 540 540 540 540 560 560 560 560 560 560 560 560 570 570 570 570 610 610 580 580 680 680 680 680 na i 48mirc 48mhz irc 511 520 545 556 563 576 a i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 22 a i rtc rtc peripheral adder measured by placing the device in vlls1 mode with external 32 khz crystal enabled by means of the rtc_cr[osce] bit and the rtc alarm set for 1 minute. includes erclk32k (32 khz external crystal) power consumption. 432 357 388 475 532 810 na i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 214 66 234 66 246 66 254 66 260 66 268 a i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 45 a i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 366 366 366 366 366 366 a general kinetis k66 sub-family, rev. 4, 04/2017 11 nxp semiconductors 2.2.5 power consumption operating behaviors note the maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma) table 7. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_run run mode current all peripheral clocks disabled, code executing from flash ? @ 1.8v ? @ 3.0v 32.3 32.4 71.03 71.81 ma ma 2 i dd_run run mode current all peripheral clocks enabled, code executing from flash ? @ 1.8v ? @ 3.0v ? @ 25c ? @ 105c 50.5 50.6 69.7 89.58 55.95 99.85 ma ma ma 3 , 4 i dd_runc o run mode current in compute operation - 120 mhz core / 24 mhz flash / bus clock disabled, code of while(1) loop executing from flash ? at 3.0 v 28.5 67.74 ma 5 i dd_hsrun run mode current all peripheral clocks disabled, code executing from flash ? @ 1.8v ? @ 3.0v 47.2 47.3 91.25 91.62 ma ma 6 i dd_hsrun run mode current all peripheral clocks enabled, code executing from flash ? @ 1.8v ? @ 3.0v ? @ 25c ? @ 105c 71.4 71.5 93.3 103.58 79.13 115.08 ma ma ma 7 , 4 i dd_hsrun co hsrun mode current in compute operation C 168 mhz core/ 28 mhz flash / bus clock disabled, code of while(1) loop executing from flash at 3.0v 42.9 91.97 ma 5 i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled 16.9 45.2 ma 8 table continues on the next page... general 12 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors table 7. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks enabled 35 62.81 ma 8 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 1.1 9.56 ma 9 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 2 9.88 ma 10 i dd_vlprc o very-low-power run mode current in compute operation - 4 mhz core / 1 mhz flash / bus clock disabled, lptmr running with 4 mhz internal reference clock ? at 3.0 v 986 9.47 a 11 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled 0.690 9.25 ma 12 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks enabled 1.5 10.00 ma i dd_stop stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 0.791 3.8 13.2 2.39 6.91 18.91 ma ma ma i dd_vlps very-low-power stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 202 1400 5100 353.77 2464.54 8949.06 a a a i dd_lls3 low leakage stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 9.0 76.3 402 16.5 88.63 656.08 a a a i dd_lls2 low leakage stop mode current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 5.7 41.3 229 9.7 55.80 276.81 a a a i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 5.5 46.3 249 7.31 58.33 380.77 a a a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 2.7 13.1 76.6 3.24 18.72 84.77 a a a table continues on the next page... general kinetis k66 sub-family, rev. 4, 04/2017 13 nxp semiconductors table 7. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 0.847 6.5 46.7 1.48 11.31 81.78 a a a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit enabled ? @ C40 to 25c ? @ 70c ? @ 105c 0.551 6.3 49.6 .65 7.12 53.68 a a a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit disabled ? @ C40 to 25c ? @ 70c ? @ 105c 0.254 6.3 48.7 0.445 10.99 85.27 a a a i dd_vbat average current with rtc and 32khz disabled at 3.0 v ? @ C40 to 25c ? @ 70c ? @ 105c 0.19 0.49 2.2 0.22 0.64 3.2 a a a i dd_vbat average current when cpu is not accessing rtc registers ? @ 1.8v ? @ C40 to 25c ? @ 70c ? @ 105c ? @ 3.0v ? @ C40 to 25c ? @ 70c ? @ 105c 0.68 1.2 3.6 0.81 1.45 4.3 0.8 1.56 5.3 0.96 1.89 6.33 a a a a a a 13 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 2. 120 mhz core and system clock, 60 mhz bus and flexbus clock, and 24 mhz flash clock. mcg configured for pee mode. all peripheral clocks disabled. 3. 120 mhz core and system clock, 60 mhz bus and flexbus clock, and 24 mhz flash clock. mcg configured for pee mode. all peripheral clocks enabled. 4. max values are measured with cpu executing dsp instructions. 5. mcg configured for pee mode. 6. 168 mhz core and system clock, 56 mhz bus and flexbus clock, and 28 mhz flash clock. mcg configured for pee mode. all peripheral clocks disabled. 7. 168 mhz core and system clock, 56 mhz bus and flexbus clock, and 28 mhz flash clock. mcg configured for pee mode. all peripheral clocks enabled. general 14 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 8. 120 mhz core and system clock, 60mhz bus clock, and flexbus. mcg configured for pee mode. 9. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash. 10. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 11. mcg configured for blpi mode. coremark benchmark compiled using iar 6.40 with optimization level high, optimized for balanced. 12. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 13. includes 32khz oscillator current and rtc operation. 2.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? usb regulator disabled ? no gpios toggled ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfe figure 3. run mode supply current vs. core frequency general kinetis k66 sub-family, rev. 4, 04/2017 15 nxp semiconductors figure 4. vlpr mode supply current vs. core frequency 2.2.6 emc radiated emissions operating behaviors table 8. emc radiated emissions operating behaviors symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 23 dbv 1 , 2 v re2 radiated emissions voltage, band 2 50C150 27 dbv v re3 radiated emissions voltage, band 3 150C500 28 dbv v re4 radiated emissions voltage, band 4 500C1000 14 dbv v re_iec iec level 0.15C1000 k 2 , 3 1. determined according to iec standard 61967-1, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 61967-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and wideband tem cell method . measurements were made while the microcontroller was running basic application code. general 16 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. v dd = 3.3 v, t a = 25 c, f osc = 12 mhz (crystal), f sys = mhz, f bus = mhz 3. specified according to annex d of iec standard 61967-2, measurement of radiated emissionstem cell and wideband tem cell method 2.2.7 designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions. 1. go to nxp.com 2. perform a keyword search for emc design. 2.2.8 capacitance attributes table 9. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 2.3 switching specifications 2.3.1 device clock specifications table 10. device clock specifications symbol description min. max. unit notes high speed run mode f sys system and core clock 180 mhz normal run mode (and high speed run mode unless otherwise specified above) f sys system and core clock 120 mhz system and core clock when full speed usb in operation 20 mhz f sys_usbhs system and core clock when high speed usb in operation 100 mhz f enet system and core clock when ethernet in operation ? 10 mbps ? 100 mbps 5 50 mhz table continues on the next page... general kinetis k66 sub-family, rev. 4, 04/2017 17 nxp semiconductors table 10. device clock specifications (continued) symbol description min. max. unit notes f bus bus clock 60 mhz fb_clk flexbus clock 60 mhz f flash flash clock 28 mhz f lptmr lptmr clock 25 mhz vlpr mode 1 f sys system and core clock 4 mhz f bus bus clock 4 mhz fb_clk flexbus clock 4 mhz f flash flash clock 1 mhz f erclk external reference clock 16 mhz f lptmr_pin lptmr clock 25 mhz f flexcan_erclk flexcan external reference clock 8 mhz f i2s_mclk i2s master clock 12.5 mhz f i2s_bclk i2s bit clock 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 2.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, can, cmt, ieee 1588 timer, timers, and i 2 c signals. table 11. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns 3 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 50 ns 3 external reset pulse width (digital glitch filter disabled) 100 ns 3 mode select ( ezp_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time (high drive strength) ? slew enabled 25 15 ns ns 4 table continues on the next page... general 18 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors table 11. general switching specifications (continued) symbol description min. max. unit notes ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 7 7 ns ns port rise and fall time (low drive strength) ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 25 15 7 7 ns ns ns ns 5 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop, vlps, lls, and vllsx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. the greater synchronous and asynchronous timing must be met. 3. this is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in stop, vlps, lls, and vllsx modes. 4. 75 pf load 5. 15 pf load 2.4 thermal specifications 2.4.1 thermal operating requirements table 12. thermal operating requirements symbol description min. max. unit notes t j die junction temperature C40 125 c t a ambient temperature C40 105 c 1 1. maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + r ja x chip power dissipation. general kinetis k66 sub-family, rev. 4, 04/2017 19 nxp semiconductors 2.4.2 thermal attributes board type symbol description 144 lqfp 144 mapbga unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 45 48 c/w 1 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 36 29 c/w 1 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 36 38 c/w 1 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 30 25 c/w 1 r jb thermal resistance, junction to board 24 16 c/w 2 r jc thermal resistance, junction to case 9 9 c/w 3 jt thermal characterization parameter, junction to package top outside center (natural convection) 2 2 c/w 4 1. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) , or eia/jedec standard jesd51-6, integrated circuit thermal test method environmental conditionsforced convection (moving air) . 2. determined according to jedec standard jesd51-8, integrated circuit thermal test method environmental conditionsjunction-to-board . 3. determined according to method 1012.1 of mil-std 883, test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. 4. determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . general 20 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 3 peripheral operating requirements and behaviors 3.1 core modules 3.1.1 debug trace timing specifications table 13. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ns t wh high pulse width 2 ns t r clock and data rise time 3 ns t f clock and data fall time 3 ns t s data setup 1.5 ns t h data hold 1.0 ns traceclk t r t wh t f t cyc t wl figure 5. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 6. trace data specifications peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 21 nxp semiconductors 3.1.2 jtag electricals table 14. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 25 50 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 20 10 ns ns ns j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.0 ns j7 tclk low to boundary scan output data valid 28 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1 ns j11 tclk low to tdo data valid 19 ns j12 tclk low to tdo high-z 17 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns table 15. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 25 12.5 ns ns ns table continues on the next page... peripheral operating requirements and behaviors 22 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors table 15. jtag full voltage range electricals (continued) symbol description min. max. unit j4 tclk rise and fall times 3 ns j5 boundary scan input data setup time to tclk rise 20 ns j6 boundary scan input data hold time after tclk rise 2.0 ns j7 tclk low to boundary scan output data valid 30.6 ns j8 tclk low to boundary scan output high-z 25 ns j9 tms, tdi input data setup time to tclk rise 8 ns j10 tms, tdi input data hold time after tclk rise 1.0 ns j11 tclk low to tdo data valid 19.0 ns j12 tclk low to tdo high-z 17.0 ns j13 trst assert time 100 ns j14 trst setup time (negation) to tclk high 8 ns j2 j3 j3 j4 j4 tclk (input) figure 7. test clock input timing j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs figure 8. boundary scan (jtag) timing peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 23 nxp semiconductors j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo figure 9. test access port timing j14 j13 tclk trst figure 10. trst timing 3.2 system modules there are no specifications necessary for the device's system modules. 3.3 clock modules peripheral operating requirements and behaviors 24 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 3.3.1 mcg specifications table 16. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) factory trimmed at nominal vdd and 25 c 32.768 khz f ints_t internal reference frequency (slow clock) user trimmed 31.25 39.0625 khz i ints internal reference (slow clock) current 20 a f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim and scftrim 0.3 0.6 %f dco 1 f dco_res_t resolution of trimmed average dco output frequency at fixed voltage and temperature using sctrim only 0.2 0.5 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over voltage and temperature 0.5 2 %f dco 1 f dco_t total deviation of trimmed average dco output frequency over fixed voltage and temperature range of 0C70c 0.3 1.5 %f dco 1 f intf_ft internal reference frequency (fast clock) factory trimmed at nominal vdd and 25c 4 mhz f intf_t internal reference frequency (fast clock) user trimmed at nominal vdd and 25 c 3 5 mhz i intf internal reference (fast clock) current 25 a f loc_low loss of external clock minimum frequency range = 00 ext clk freq: above (3/5)f int never reset ext clk freq: between (2/5)fint and (3/5)f int maybe reset (phase dependency) ext clk freq: below (2/5)f int always reset (3/5) x f ints_t khz f loc_high loss of external clock minimum frequency range = 01, 10, or 11 ext clk freq: above (16/5)f int never reset ext clk freq: between (15/5)f int and (16/5)f int maybe reset (phase dependency) ext clk freq: below (15/5)f int always reset (16/5) x f ints_t khz fll f fll_ref fll reference frequency range 31.25 39.0625 khz f dco_ut dco output frequency range untrimmed low range (drs=00, dmx32=0) 640 f ints_ut 16.0 23.04 26.66 mhz 2 mid range (drs=01, dmx32=0) 1280 f ints_ut 32.0 46.08 53.32 table continues on the next page... peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 25 nxp semiconductors table 16. mcg specifications (continued) symbol description min. typ. max. unit notes mid-high range (drs=10, dmx32=0) 1920 f ints_ut 48.0 69.12 79.99 high range (drs=11, dmx32=0) 2560 f ints_ut 64.0 92.16 106.65 low range (drs=00, dmx32=1) 732 f ints_ut 18.3 26.35 30.50 mid range (drs=01, dmx32=1) 1464 f ints_ut 36.6 52.70 60.99 mid-high range (drs=10, dmx32=1) 2197 f ints_ut 54.93 79.09 91.53 high range (drs=11, dmx32=1) 2929 f ints_ut 73.23 105.44 122.02 f dco dco output frequency range low range (drs=00) 640 f fll_ref 20 20.97 25 mhz 3 , 4 mid range (drs=01) 1280 f fll_ref 40 41.94 50 mhz mid-high range (drs=10) 1920 f fll_ref 60 62.91 75 mhz high range (drs=11) 2560 f fll_ref 80 83.89 100 mhz f dco_t_dmx3 2 dco output frequency low range (drs=00) 732 f fll_ref 23.99 mhz 5 , 6 mid range (drs=01) 1464 f fll_ref 47.97 mhz mid-high range (drs=10) 2197 f fll_ref 71.99 mhz high range (drs=11) 2929 f fll_ref 95.98 mhz j cyc_fll fll period jitter ? f dco = 48 mhz ? f dco = 98 mhz 180 150 ps table continues on the next page... peripheral operating requirements and behaviors 26 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors table 16. mcg specifications (continued) symbol description min. typ. max. unit notes t fll_acquire fll target frequency acquisition time 1 ms 7 pll f pll_ref pll reference frequency range 8 16 mhz f vcoclk_2x vco output frequency 180 360 mhz f vcoclk pll output frequency 90 180 mhz f vcoclk_90 pll quadrature output frequency 90 180 mhz i pll pll operating current ? vco @ 184 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 23) 2.8 ma 8 i pll pll operating current ? vco @ 360 mhz (f osc_hi_1 = 32 mhz, f pll_ref = 8 mhz, vdiv multiplier = 45) 3.6 ma 8 j cyc_pll pll period jitter (rms) ? f vco = 180 mhz ? f vco = 360 mhz 100 75 ps ps 9 j acc_pll pll accumulated jitter over 1s (rms) ? f vco = 180 mhz ? f vco = 360 mhz 600 300 ps ps 9 d unl lock exit frequency tolerance 4.47 5.97 % t pll_lock lock detector detection time 150 10 -6 + 1075(1/ f pll_ref ) s 10 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. this applies when sctrim at value (0x80) and scftrim control bit at value (0x0). 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 4. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( f dco_t ) over voltage and temperature should be considered. 5. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=1. 6. the resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. this specification applies to any time the fll reference source or reference divider is changed, trim value is changed, dmx32 bit is changed, drs bits are changed, or changing from fll disabled (blpe, blpi) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 8. excludes any oscillator currents that are also consuming power while pll is in operation. 9. this specification was obtained using a nxp developed pcb. pll jitter is dependent on the noise characteristics of each pcb and results will vary. 10. this specification applies to any time the pll vco divider or reference divider is changed, or changing from pll disabled (blpe, blpi) to pll enabled (pbe, pee). if a crystal/resonator is being used as the reference, this specification assumes it is already running. peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 27 nxp semiconductors 3.3.2 irc48m specifications table 17. irc48m specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i dd48m supply current 520 a f irc48m internal reference frequency 48 mhz f irc48m_ol_lv open loop total deviation of irc48m frequency at low voltage (vdd=1.71v-1.89v) over full temperature ? regulator disable (usb_clk_recover_irc_en[reg_en]=0 ) ? regulator enable (usb_clk_recover_irc_en[reg_en]=1 ) 0.4 0.5 1.0 1.5 %f irc48m 1 f irc48m_ol_hv open loop total deviation of irc48m frequency at high voltage (vdd=1.89v-3.6v) over 070c ? regulator enable (usb_clk_recover_irc_en[reg_en]=1 ) 0.2 0.5 %f irc48m 1 f irc48m_ol_hv open loop total deviation of irc48m frequency at high voltage (vdd=1.89v-3.6v) over full temperature ? regulator enable (usb_clk_recover_irc_en[reg_en]=1 ) 0.4 1.0 %f irc48m 1 f irc48m_cl closed loop total deviation of irc48m frequency over voltage and temperature 0.1 %f host 2 j cyc_irc48m period jitter (rms) 35 150 ps t irc48mst startup time 2 3 s 3 1. the maximum value represents characterized results equivalent to mean plus or minus three times the standard deviation (mean 3 sigma) 2. closed loop operation of the irc48m is only feasible for usb device operation; it is not usable for usb host operation. it is enabled by configuring for usb device, selecting irc48m as usb clock source, and enabling the clock recover function (usb_clk_recover_irc_ctrl[clock_recover_en]=1, usb_clk_recover_irc_en[irc_en]=1). 3. irc48m startup time is defined as the time between clock enablement and clock availability for system use. enable the clock by one of the following settings: ? usb_clk_recover_irc_en[irc_en]=1, or ? mcg_c7[oscsel]=10, or ? sim_sopt2[pllfllsel]=11 3.3.3 oscillator electrical specifications peripheral operating requirements and behaviors 28 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 3.3.3.1 oscillator dc electrical specifications table 18. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 600 200 300 950 1.2 1.5 na a a a ma ma 1 i ddosc supply current high gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz 7.5 500 650 2.5 3.25 4 a a a ma ma ma 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode (hgo=0) m 2 , 4 feedback resistor low-frequency, high-gain mode (hgo=1) 10 m feedback resistor high-frequency, low- power mode (hgo=0) m feedback resistor high-frequency, high-gain mode (hgo=1) 1 m r s series resistor low-frequency, low-power mode (hgo=0) k series resistor low-frequency, high-gain mode (hgo=1) 200 k series resistor high-frequency, low-power mode (hgo=0) k series resistor high-frequency, high-gain mode (hgo=1) 0 k v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode (hgo=0) 0.6 v table continues on the next page... peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 29 nxp semiconductors table 18. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, high-gain mode (hgo=1) v dd v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, low-power mode (hgo=0) 0.6 v peak-to-peak amplitude of oscillation (oscillator mode) high-frequency, high-gain mode (hgo=1) v dd v 1. v dd =3.3 v, temperature =25 c, internal capacitance = 20 pf 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.3.2 oscillator frequency specifications table 19. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low- frequency mode (mcg_c2[range]=00) 32 40 khz f osc_hi_1 oscillator crystal or resonator frequency high- frequency mode (low range) (mcg_c2[range]=01) 3 8 mhz f osc_hi_2 oscillator crystal or resonator frequency high frequency mode (high range) (mcg_c2[range]=1x) 8 32 mhz f ec_extal input clock frequency (external clock mode) 50 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode (hgo=0) 750 ms 3 , 4 crystal startup time 32 khz low-frequency, high-gain mode (hgo=1) 250 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) 0.6 ms crystal startup time 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) 1 ms 1. other frequency limits may apply when external clock is being used as a reference for the fll or pll. 2. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. peripheral operating requirements and behaviors 30 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. note the 32 khz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 3.3.4 32 khz oscillator electrical characteristics 3.3.4.1 32 khz oscillator dc electrical specifications table 20. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m c para parasitical capacitance of extal32 and xtal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the extal32 and xtal32 pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.4.2 32 khz oscillator frequency specifications table 21. 32 khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 f ec_extal32 externally provided input clock frequency 32.768 khz 2 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2 , 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to extal32 and does not apply to any other clock input. the oscillator remains enabled and xtal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . 3.4 memories and memory interfaces peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 31 nxp semiconductors 3.4.1 flash (ftfe) electrical specifications this section describes the electrical characteristics of the ftfe module. 3.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 22. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm8 program phrase high-voltage time 7.5 18 s t hversscr erase flash sector high-voltage time 13 113 ms 1 t hversblk256k erase flash block high-voltage time for 256 kb 208 1808 ms 1 t hversblk512k erase flash block high-voltage time for 512 kb 416 3616 ms 1 1. maximum time based on expectations at cycling end-of-life. 3.4.1.2 flash timing specifications commands table 23. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk256k t rd1blk512k read 1s block execution time ? 256 kb data flash ? 512 kb program flash 1.0 1.8 ms ms t rd1sec4k read 1s section execution time (4 kb flash) 100 s 1 t pgmchk program check execution time 95 s 1 t rdrsrc read resource execution time 40 s 1 t pgm8 program phrase execution time 90 150 s t ersblk256k t ersblk512k erase flash block execution time ? 256 kb data flash ? 512 kb program flash 220 435 1850 3700 ms ms 2 t ersscr erase flash sector execution time 15 115 ms 2 t pgmsec1k program section execution time (1 kb flash) 5 ms t rd1allx t rd1alln read 1s all blocks execution time ? flexnvm devices ? program flash only devices 5.9 6.7 ms ms t rdonce read once execution time 30 s 1 t pgmonce program once execution time 90 s t ersall erase all blocks execution time 1750 14,800 ms 2 table continues on the next page... peripheral operating requirements and behaviors 32 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors table 23. flash command timing specifications (continued) symbol description min. typ. max. unit notes t vfykey verify backdoor access key execution time 30 s 1 t swapx01 t swapx02 t swapx04 t swapx08 t swapx10 swap control execution time ? control code 0x01 ? control code 0x02 ? control code 0x04 ? control code 0x08 ? control code 0x10 200 90 90 90 150 150 30 150 s s s s s t pgmpart32k t pgmpart256k program partition for eeprom execution time ? 32 kb eeprom backup ? 256 kb eeprom backup 70 78 ms ms t setramff t setram32k t setram64k t setram128k t setram256k set flexram function execution time: ? control code 0xff ? 32 kb eeprom backup ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup 70 0.8 1.3 2.4 4.5 1.2 1.9 3.1 5.5 s ms ms ms ms t eewr8b32k t eewr8b64k t eewr8b128k t eewr8b256k byte-write to flexram execution time: ? 32 kb eeprom backup ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup 385 475 650 1000 1700 2000 2350 3250 s s s s t eewr16b32k t eewr16b64k t eewr16b128k t eewr16b256k 16-bit write to flexram execution time: ? 32 kb eeprom backup ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup 385 475 650 1000 1700 2000 2350 3250 s s s s t eewr32bers 32-bit write to erased flexram location execution time 360 1500 s t eewr32b32k t eewr32b64k t eewr32b128k t eewr32b256k 32-bit write to flexram execution time: ? 32 kb eeprom backup ? 64 kb eeprom backup ? 128 kb eeprom backup ? 256 kb eeprom backup 630 810 1200 1900 2000 2250 2650 3500 s s s s 1. assumes 25mhz or greater flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 33 nxp semiconductors 3.4.1.3 flash high voltage current behaviors table 24. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 3.5 7.5 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 3.4.1.4 reliability specifications table 25. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 data flash t nvmretd10k data retention after up to 10 k cycles 5 50 years t nvmretd1k data retention after up to 1 k cycles 20 100 years n nvmcycd cycling endurance 10 k 50 k cycles 2 flexram as eeprom t nvmretee100 data retention up to 100% of write endurance 5 50 years t nvmretee10 data retention up to 10% of write endurance 20 100 years n nvmcycee cycling endurance for eeprom backup 20 k 50 k cycles 2 n nvmwree16 n nvmwree128 n nvmwree512 n nvmwree2k n nvmwree8k write endurance ? eeprom backup to flexram ratio = 16 ? eeprom backup to flexram ratio = 128 ? eeprom backup to flexram ratio = 512 ? eeprom backup to flexram ratio = 2,048 ? eeprom backup to flexram ratio = 8,192 140 k 1.26 m 5 m 20 m 80 m 400 k 3.2 m 12.8 m 50 m 200 m writes writes writes writes writes 3 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40c t j 125c. 3. write endurance represents the number of writes to each flexram location at -40c tj 125c influenced by the cycling endurance of the flexnvm and the allocated eeprom backup per subsystem. minimum and typical values assume all 16-bit or 32-bit writes to flexram; all 8-bit writes result in 50% less endurance. peripheral operating requirements and behaviors 34 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 3.4.1.5 write endurance to flexram for eeprom when the flexnvm partition code is not set to full data flash, the eeprom data set size can be set to any of several non-zero values. the bytes not assigned to data flash via the flexnvm partition code are used by the ftfe to obtain an effective endurance increase for the eeprom data. the built-in eeprom record management system raises the number of program/erase cycles that can be attained prior to device wear-out by cycling the eeprom data through a larger eeprom nvm storage space. while different partitions of the flexnvm are available, the intention is that a single choice for the flexnvm partition code and eeprom data set size is used throughout the entire lifetime of a given application. the eeprom endurance equation and graph shown below assume that only one configuration is ever used. writes_subsystem = write_efficiency n eeprom C 2 eeesplit eeesize eeesplit eeesize nvmcycee where ? writes_subsystem minimum number of writes to each flexram location for subsystem (each subsystem can have different endurance) ? eeprom allocated flexnvm for each eeprom subsystem based on depart; entered with the program partition command ? eeesplit flexram split factor for subsystem; entered with the program partition command ? eeesize allocated flexram based on depart; entered with the program partition command ? write_efficiency ? 0.25 for 8-bit writes to flexram ? 0.50 for 16-bit or 32-bit writes to flexram ? n nvmcycee eeprom-backup cycling endurance peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 35 nxp semiconductors 16/32-bit 8-bit ratio of eeprom backup to flexram average writes per flexram location figure 11. eeprom backup writes to flexram 3.4.2 ezport switching specifications table 26. ezport full voltage range switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) f sys /2 mhz ep1a ezp_ck frequency of operation (read command) f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ns ep3 ezp_cs input valid to ezp_ck high (setup) 5 ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ns ep7 ezp_ck low to ezp_q output valid 14 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ns ep9 ezp_cs negation to ezp_q tri-state 12 ns peripheral operating requirements and behaviors 36 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) figure 12. ezport timing diagram 3.4.3 flexbus switching specifications all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 27. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 11.8 ns fb3 address, data, and control output hold 1.0 ns 1 fb4 data and fb_ta input setup 11.9 ns fb5 data and fb_ta input hold 0.0 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 37 nxp semiconductors 2. specification is valid for all fb_ad[31:0] and fb_ta. table 28. flexbus full voltage range switching specifications num description min. max. unit notes operating voltage 1.71 3.6 v frequency of operation fb_clk mhz fb1 clock period 1/fb_clk ns fb2 address, data, and control output valid 12.6 ns fb3 address, data, and control output hold 1.0 ns 1 fb4 data and fb_ta input setup 12.5 ns fb5 data and fb_ta input hold 0 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fb_cs n , fb_oe, fb_r/ w, fb_tbst, fb_tsiz[1:0], fb_ale, and fb_ts. 2. specification is valid for all fb_ad[31:0] and fb_ta. peripheral operating requirements and behaviors 38 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors address address data tsiz aa=1 aa=0 aa=1 aa=0 fb3 fb5 fb4 fb4 fb5 fb1 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] fb2 read timing parameters electricals_read.svg s0 s1 s2 s3 s0 s0 s1 s2 s3 s0 figure 13. flexbus read timing diagram peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 39 nxp semiconductors address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] write timing parameters electricals_write.svg figure 14. flexbus write timing diagram 3.4.4 sdram controller specifications following figure shows sdram read cycle. peripheral operating requirements and behaviors 40 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors a[23:0] sras d[31:16] actv nop sdram_cs [1:0] read column clkout 0 dramw bs [3:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 d1 d2 d4 d6 d5 d4 1 1 nop d4 row d3 pre d0 scas dacr[casl] = 2 figure 15. sdram read timing diagram table 29. sdram timing (full voltage range) num characteristic 1 symbol min max unit operating voltage 1.71 3.6 v frequency of operation clkout mhz d0 clock period 1/clkout ns 2 d1 clkout high to sdram address valid t chdav - 11.2 ns d2 clkout high to sdram control valid t chdcv 11.1 ns d3 clkout high to sdram address invalid t chdai 1.0 - ns d4 clkout high to sdram control invalid t chdci 1.0 - ns d5 sdram data valid to clkout high t ddvch 12.0 - ns d6 clkout high to sdram data invalid t chddi 1.0 - ns d7 3 clkout high to sdram data valid t chddvw - 12.0 ns d8 3 clkout high to sdram data invalid t chddiw 1.0 - ns 1. all timing specifications are based on taking into account, a 25pf load on the sdram output pins. 2. clkout is same as fb_clk, maximum frequency can be 60 mhz peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 41 nxp semiconductors 3. d7 and d8 are for write cycles only. table 30. sdram timing (limited voltage range) num characteristic 1 symbol min max unit operating voltage 2.7 3.6 v frequency of operation clkout mhz d0 clock period 1/clkout ns 2 d1 clkout high to sdram address valid t chdav - 11.1 ns d2 clkout high to sdram control valid t chdcv 11.1 ns d3 clkout high to sdram address invalid t chdai 1.0 - ns d4 clkout high to sdram control invalid t chdci 1.0 - ns d5 sdram data valid to clkout high t ddvch 11.3 - ns d6 clkout high to sdram data invalid t chddi 1.0 - ns d7 3 clkout high to sdram data valid t chddvw - 11.1 ns d8 3 clkout high to sdram data invalid t chddiw 1.0 - ns 1. all timing specifications are based on taking into account, a 25pf load on the sdram output pins. 2. clkout is same as fb_clk, maximum frequency can be 60 mhz 3. d7 and d8 are for write cycles only. following figure shows an sdram write cycle. peripheral operating requirements and behaviors 42 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors a[23:0] sras scas 1 d[31:16] actv pallnop sdram_cs [1:0] write row column clkout dramw bs [3:0] d1 d2 d4 d8 d4 0 1 2 3 4 5 6 7 8 9 10 11 12 d7 nop 1 dacr[casl] = 2 d4 d3 d2 d4 d0 figure 16. sdram write timing diagram 3.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 3.6 analog 3.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 31 and table 32 are achievable on the differential pins adcx_dp0, adcx_dm0. peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 43 nxp semiconductors all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.6.1.1 16-bit adc operating conditions table 31. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v v refl adc reference voltage low v ssa v ssa v ssa v v adin input voltage ? 16-bit differential mode ? all other modes vrefl vrefl 31/32 * vrefh vrefh v c adin input capacitance ? 16-bit mode ? 8-bit / 10-bit / 12-bit modes 8 4 10 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 13-bit / 12-bit modes f adck < 4 mhz 5 k 3 f adck adc conversion clock frequency 13-bit mode 1.0 24 mhz 4 f adck adc conversion clock frequency 16-bit mode 2.0 12.0 mhz 4 c rate adc conversion rate 13-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 1200 ks/s 5 c rate adc conversion rate 16-bit mode no adc hardware averaging continuous conversions enabled, subsequent conversion time 37.037 461.467 ks/s 5 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. peripheral operating requirements and behaviors 44 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool . r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 17. adc input impedance equivalency diagram 3.6.1.2 16-bit adc electrical characteristics table 32. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 table continues on the next page... peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 45 nxp semiconductors table 32. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes inl integral non-linearity ? 12-bit modes ? <12-bit modes 1.0 0.5 C2.7 to +1.9 C0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? 13-bit modes C1 to 0 0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 enob + 1.76 db thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 -94 -85 db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 82 78 95 90 db db 7 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 8 v temp25 temp sensor voltage 25 c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda peripheral operating requirements and behaviors 46 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 8. adc conversion clock < 3 mhz typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 1211 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples figure 18. typical enob vs. adc_clk for 16-bit differential mode typical adc 16-bit single-ended enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 14.00 13.75 13.25 13.00 12.75 12.50 12.00 11.75 11.50 11.25 11.00 1 2 3 4 5 6 7 8 9 10 1211 averaging of 4 samples averaging of 32 samples 13.50 12.25 figure 19. typical enob vs. adc_clk for 16-bit single-ended mode peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 47 nxp semiconductors 3.6.2 cmp and 6-bit dac electrical specifications table 33. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd C0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 peripheral operating requirements and behaviors 48 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.82.5 2.2 1.91.61.3 1 0.70.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 figure 20. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 49 nxp semiconductors 00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) figure 21. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 3.6.3 12-bit dac electrical characteristics 3.6.3.1 12-bit dac operating requirements table 34. 12-bit dac operating requirements symbol desciption min. max. unit notes v dda supply voltage 3.6 v v dacr reference voltage 1.13 3.6 v 1 c l output load capacitance 100 pf 2 i l output load current 1 ma 1. the dac reference can be selected to be v dda or v refh . 2. a small load capacitance (47 pf) can improve the bandwidth performance of the dac. peripheral operating requirements and behaviors 50 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 3.6.3.2 12-bit dac operating behaviors table 35. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current low-power mode 150 a i dda_dach p supply current high-speed mode 700 a t daclp full-scale settling time (0x080 to 0xf7f) low-power mode 100 200 s 1 t dachp full-scale settling time (0x080 to 0xf7f) high-power mode 15 30 s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) low-power mode and high- speed mode 0.7 1 s 1 v dacoutl dac output voltage range low high- speed mode, no load, dac set to 0x000 100 mv v dacouth dac output voltage range high high- speed mode, no load, dac set to 0xfff v dacr ?100 v dacr mv inl integral non-linearity error high speed mode 8 lsb 2 dnl differential non-linearity error v dacr > 2 v 1 lsb 3 dnl differential non-linearity error v dacr = vref_out 1 lsb 4 v offset offset error 0.4 0.8 %fsr 5 e g gain error 0.1 0.6 %fsr 5 psrr power supply rejection ratio, v dda 2.4 v 60 90 db t co temperature coefficient offset voltage 3.7 v/c 6 t ge temperature coefficient gain error 0.000421 %fsr/c a c offset aging coefficient 100 v/yr rop output resistance (load = 3 k) 250 sr slew rate -80h f7fh 80h ? high power (sp hp ) ? low power (sp lp ) 1.2 0.05 1.7 0.12 v/s ct channel to channel cross talk -80 db bw 3db bandwidth ? high power (sp hp ) ? low power (sp lp ) 550 40 khz 1. settling within 1 lsb 2. the inl is measured for 0 + 100 mv to v dacr ?100 mv 3. the dnl is measured for 0 + 100 mv to v dacr ?100 mv 4. the dnl is measured for 0 + 100 mv to v dacr ?100 mv with v dda > 2.4 v 5. calculated by a best fit curve from v ss + 100 mv to v dacr ? 100 mv peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 51 nxp semiconductors 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 figure 22. typical inl error vs. digital code peripheral operating requirements and behaviors 52 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 figure 23. offset at half scale vs. temperature 3.6.4 voltage reference electrical specifications table 36. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 3.6 v t a temperature operating temperature range of the device c c l output load capacitance 100 nf 1 , 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 53 nxp semiconductors table 37. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.190 1.195 1.200 v 1 v out voltage reference output factory trim 1.1584 1.2376 v 1 v out voltage reference output user trim 1.193 1.197 v 1 v step voltage reference trim step 0.5 mv 1 v tdrift temperature drift (vmax -vmin across the full temperature range) 80 mv 1 ac aging coefficient 400 uv/yr i bg bandgap only current 80 a 1 v load load regulation ? current = 1.0 ma 200 v 1 , 2 t stup buffer startup time 100 s t chop_osc_st up internal bandgap start-up delay with chop oscillator enabled 35 ms v vdrift voltage drift (vmax -vmin across the full voltage range) 2 mv 1 1. see the chip's reference manual for the appropriate settings of the vref status and control register. 2. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load table 38. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 39. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim 1.173 1.225 v 3.7 timers see general switching specifications . 3.8 communication interfaces peripheral operating requirements and behaviors 54 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 3.8.1 ethernet switching specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 3.8.1.1 mii signal switching specifications the following timing specs meet the requirements for mii style interfaces for a range of transceiver devices. table 40. mii signal switching specifications (limited voltage range) symbol description min. max. unit operating voltage 2.7 3.6 v rxclk frequency 25 mhz mii1 rxclk pulse width high 35% 65% rxclk period mii2 rxclk pulse width low 35% 65% rxclk period mii3 rxd[3:0], rxdv, rxer to rxclk setup 5 ns mii4 rxclk to rxd[3:0], rxdv, rxer hold 5 ns txclk frequency 25 mhz mii5 txclk pulse width high 35% 65% txclk period mii6 txclk pulse width low 35% 65% txclk period mii7 txclk to txd[3:0], txen, txer invalid 2 ns mii8 txclk to txd[3:0], txen, txer valid 25 ns table 41. mii signal switching specifications (full voltage range) symbol description min. max. unit operating voltage 1.7 3.6 v rxclk frequency 25 mhz mii1 rxclk pulse width high 35% 65% rxclk period mii2 rxclk pulse width low 35% 65% rxclk period mii3 rxd[3:0], rxdv, rxer to rxclk setup 5 ns table continues on the next page... peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 55 nxp semiconductors table 41. mii signal switching specifications (full voltage range) (continued) symbol description min. max. unit mii4 rxclk to rxd[3:0], rxdv, rxer hold 5 ns txclk frequency 25 mhz mii5 txclk pulse width high 35% 65% txclk period mii6 txclk pulse width low 35% 65% txclk period mii7 txclk to txd[3:0], txen, txer invalid 2 ns mii8 txclk to txd[3:0], txen, txer valid 25 ns mii7mii8 valid data valid data valid data mii6 mii5 txclk (input) txd[n:0] txen txer figure 24. rmii/mii transmit signal timing diagram mii2 mii1 mii4mii3 valid data valid data valid data rxclk (input) rxd[n:0] rxdv rxer figure 25. rmii/mii receive signal timing diagram peripheral operating requirements and behaviors 56 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 3.8.1.2 rmii signal switching specifications the following timing specs meet the requirements for rmii style interfaces for a range of transceiver devices. table 42. rmii signal switching specifications (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 extal frequency (rmii input clock rmii_clk) 50 mhz rmii1 rmii_clk pulse width high 35% 65% rmii_clk period rmii2 rmii_clk pulse width low 35% 65% rmii_clk period rmii3 rxd[1:0], crs_dv, rxer to rmii_clk setup 4 ns rmii4 rmii_clk to rxd[1:0], crs_dv, rxer hold 2 ns rmii7 rmii_clk to txd[1:0], txen invalid 4 ns rmii8 rmii_clk to txd[1:0], txen valid 15.4 ns table 43. rmii signal switching specifications (full voltage range) num description min. max. unit operating voltage 1.7 3.6 extal frequency (rmii input clock rmii_clk) 50 mhz rmii1 rmii_clk pulse width high 35% 65% rmii_clk period rmii2 rmii_clk pulse width low 35% 65% rmii_clk period rmii3 rxd[1:0], crs_dv, rxer to rmii_clk setup 4 ns rmii4 rmii_clk to rxd[1:0], crs_dv, rxer hold 2 ns rmii7 rmii_clk to txd[1:0], txen invalid 4 ns rmii8 rmii_clk to txd[1:0], txen valid 17.5 ns 3.8.1.3 mdio serial management timing specifications table 44. mdio serial management channel signal timing num characteristic symbol min max unit e10 mdc cycle time t mdc 400 ns e11 mdc pulse width 40 60 % t mdc e12 mdc to mdio output valid 375 ns e13 mdc to mdio output invalid 25 ns e14 mdio input to mdc setup 10 ns e15 mdio input to mdc hold 0 ns peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 57 nxp semiconductors e11 e10 e11 e12 valid data e13 e14 e15 valid data mdc (output) mdio (output) mdio (input) figure 26. mdio serial management channel timing diagram 3.8.2 usb voltage regulator electrical specifications table 45. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vreg_in0 vreg_in1 regulator selectable input supply voltages 2.7 5.5 v 2 i ddon vreg_in0 vreg_in1 quiescent current run mode, load current equal zero, input supply (vreg_in*) > 3.6 v 157 157 a i ddstby vreg_in0 vreg_in1 quiescent current standby mode, load current equal zero 2 2 a i ddoff vreg_in0 vreg_in1 quiescent current shutdown mode ? vreg_in*= 5.0 v and temperature=25 c 680 920 na i loadrun maximum load current run mode 150 ma 3 i loadstby maximum load current standby mode 1 ma v dropout regulator drop-out voltage run mode at maximum load current with inrush current limit disabled 300 mv vreg_out regulator programmable output target voltage selected input supply > programmed output target voltage + v dropout ? run mode ? standby mode 3 2.1 3.3 2.8 3.6 3.6 v v 4 table continues on the next page... peripheral operating requirements and behaviors 58 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors table 45. usb vreg electrical specifications (continued) symbol description min. typ. 1 max. unit notes c out external output capacitor 1.76 2.2 8.16 f esr external output capacitor equivalent series resistance 1 100 m i lim short circuit current 350 ma 5 i inrush inrush current limit 40 100 ma 6 , 7 , 8 , 9 , 10 1. typical values assume the selected input supply is 5.0 v, temp = 25 c unless otherwise stated. 2. operation range is 2.7 v to 5.5 v; tolerance voltage is up to 6 v. 3. 150ma is inclusive of the run mode current of the on-chip usb modules. available load outside of the chip depends on usb operation and device power dissipation limits. 4. the target voltage for the regulator is programmable, accounting for the range of the max and min values 5. current limit disabled. 6. current limit should be disabled after the powers have stabilized to allow full functionality of the regulator. 7. limited characterization 8. i inrush with vreginx=4.0 v to 5.5 v 9. the minimum value of i inrush is stated for operation when only one of vreg_in0 / vreg_in1 is powered, or when vreg_in0 and vreg_in1 both have the same voltage level. when vreg_in0 and vreg_in1 are operated at different voltage levels with the selected vreg_in lower than the non-selected vreg_in, the minumum value of i inrush may decrease to a lower value. 10. total current load on startup should be less than i inrush min over full input voltage range of the regulator. 3.8.3 usb full speed transceiver and high speed phy specifications this section describes the usb0 port full speed/low speed transceiver and usb1 port usb-phy high speed phy parameters. the high speed phy is capable of full and low speed signalling as well. the usb0 (fs/ls transceiver) and usb1 ((usb hs/fs/ls) meet the electrical compliance requirements defined in the universal serial bus revision 2.0 specification with the amendments below. ? usb engineering change notice ? title: 5v short circuit withstand requirement change ? applies to: universal serial bus specification, revision 2.0 ? errata for usb revision 2.0 april 27, 2000 as of 12/7/2000 ? usb engineering change notice ? title: pull-up/pull-down resistors ? applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 59 nxp semiconductors ? title: suspend current limit changes ? applies to: universal serial bus specification, revision 2.0 ? on-the-go and embedded host supplement to the usb revision 2.0 specification ? revision 2.0 version 1.1a july 27, 2012 ? battery charging specification (available from usb-if) ? revision 1.2 (including errata and ecns through march 15, 2012), march 15, 2012 usb1_vbus pin is a detector function which is 5v tolerant and complies with the above specifications without needing any external voltage division components. 3.8.4 usb dcd electrical specifications table 46. usb dcd electrical specifications symbol description min. typ. max. unit v dp_src , v dm_src usb_dp and usb_dm source voltages (up to 250 a) 0.5 0.7 v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 a i dm_sink , i dp_sink usb_dm and usb_dp sink currents 50 100 150 a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k v dat_ref data detect voltage 0.25 0.33 0.4 v 3.8.5 can switching specifications see general switching specifications . peripheral operating requirements and behaviors 60 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 3.8.6 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 47. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 2 ns 1 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 2 ns 2 ds5 dspi_sck to dspi_sout valid 15.0 ns ds6 dspi_sck to dspi_sout invalid 1.0 ns ds7 dspi_sin to dspi_sck input setup 15.8 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 2. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 27. dspi classic spi timing master mode table 48. slave mode dspi timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v frequency of operation 15 1 mhz table continues on the next page... peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 61 nxp semiconductors table 48. slave mode dspi timing (limited voltage range) (continued) num description min. max. unit ds9 dspi_sck input cycle time 4 x t bus ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid 23.0 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2.7 ns ds14 dspi_sck to dspi_sin input hold 7.0 ns ds15 dspi_ss active to dspi_sout driven 13 ns ds16 dspi_ss inactive to dspi_sout not driven 13 ns 1. the maximum operating frequency is measured with non-continuous cs and sck. when dspi is configured with continuous cs and sck, there is a constraint that spi clock should not be greater than 1/6 of bus clock, for example, when bus clock is 60mhz, spi clock should not be greater than 10mhz. first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 28. dspi classic spi timing slave mode 3.8.7 dspi switching specifications (full voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 49. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 15 mhz table continues on the next page... peripheral operating requirements and behaviors 62 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors table 49. master mode dspi timing (full voltage range) (continued) num description min. max. unit notes ds1 dspi_sck output cycle time 4 x t bus ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspi_sck delay (t bus x 2) ? 4 ns 2 ds4 dspi_sck to dspi_pcs n invalid delay (t bus x 2) ? 4 ns 3 ds5 dspi_sck to dspi_sout valid 15 ns ds6 dspi_sck to dspi_sout invalid 1.0 ns ds7 dspi_sin to dspi_sck input setup 15.8 ns ds8 dspi_sck to dspi_sin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spix_ctarn[pssck] and spix_ctarn[cssck]. 3. the delay is programmable in spix_ctarn[pasc] and spix_ctarn[asc]. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout figure 29. dspi classic spi timing master mode table 50. slave mode dspi timing (full voltage range) num description min. max. unit operating voltage 1.71 3.6 v frequency of operation 7.5 mhz ds9 dspi_sck input cycle time 8 x t bus ns ds10 dspi_sck input high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds11 dspi_sck to dspi_sout valid 23.1 ns ds12 dspi_sck to dspi_sout invalid 0 ns ds13 dspi_sin to dspi_sck input setup 2.6 ns ds14 dspi_sck to dspi_sin input hold 7.0 ns ds15 dspi_ss active to dspi_sout driven 13.0 ns ds16 dspi_ss inactive to dspi_sout not driven 13.0 ns peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 63 nxp semiconductors first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin figure 30. dspi classic spi timing slave mode 3.8.8 inter-integrated circuit interface (i 2 c) timing table 51. i 2 c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.25 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd ; dat 0 1 3.45 2 0 3 0.9 1 s data set-up time t su ; dat 250 4 100 2 , 5 ns rise time of sda and scl signals t r 1000 20 +0.1c b 6 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 5 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns 1. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the sda and scl lines. 2. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 3. input signal slew = 10 ns and output load = 50 pf 4. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 5. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such peripheral operating requirements and behaviors 64 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors a device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 6. c b = total capacitance of the one bus line in pf. table 52. i 2 c 1 mbps timing characteristic symbol minimum maximum unit scl clock frequency f scl 0 1 1 mhz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 0.26 s low period of the scl clock t low 0.5 s high period of the scl clock t high 0.26 s set-up time for a repeated start condition t su ; sta 0.26 s data hold time for i 2 c bus devices t hd ; dat 0 s data set-up time t su ; dat 50 ns rise time of sda and scl signals t r 20 +0.1c b , 2 120 ns fall time of sda and scl signals t f 20 +0.1c b 2 120 ns set-up time for stop condition t su ; sto 0.26 s bus free time between stop and start condition t buf 0.5 s pulse width of spikes that must be suppressed by the input filter t sp 0 50 ns 1. the maximum scl clock frequency of 1 mbps can support maximum bus loading when using the high drive pins across the full voltage range. 2. c b = total capacitance of the one bus line in pf. ? ? sda hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r scl figure 31. timing definition for devices on the i 2 c bus 3.8.9 uart switching specifications see general switching specifications . peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 65 nxp semiconductors 3.8.10 low power uart switching specifications see general switching specifications . 3.8.11 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 53. sdhc full voltage range switching specifications num symbol description min. max. unit operating voltage 1.71 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed\high speed) 0 25\50 mhz fpp clock frequency (mmc full speed\high speed) 0 20\50 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 8.6 8.3 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns table 54. sdhc limited voltage range switching specifications num symbol description min. max. unit operating voltage 2.7 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sd\sdio full speed\high speed) 0 25\50 mhz fpp clock frequency (mmc full speed\high speed) 0 20\50 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns table continues on the next page... peripheral operating requirements and behaviors 66 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors table 54. sdhc limited voltage range switching specifications (continued) num symbol description min. max. unit sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 7.6 8.3 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5 ns sd8 t ih sdhc input hold time 0 ns sd2sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 32. sdhc timing 3.8.12 i 2 s switching specifications this section provides the ac timings for the i 2 s in master (clocks driven) and slave modes (clocks input). all timings are given for non-inverted serial clock polarity (tcr[tsckp] = 0, rcr[rsckp] = 0) and a non-inverted frame sync (tcr[tfsi] = 0, rcr[rfsi] = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (i2s_bclk) and/or the frame sync (i2s_fs) shown in the figures below. table 55. i2s master mode timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_bclk cycle time 80 ns table continues on the next page... peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 67 nxp semiconductors table 55. i2s master mode timing (limited voltage range) (continued) num description min. max. unit s4 i2s_bclk pulse width high/low 45% 55% bclk period s5 i2s_bclk to i2s_fs output valid 15 ns s6 i2s_bclk to i2s_fs output invalid 0 ns s7 i2s_bclk to i2s_txd valid 15 ns s8 i2s_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_fs input setup before i2s_bclk 15 ns s10 i2s_rxd/i2s_fs input hold after i2s_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_bclk (output) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd figure 33. i 2 s timing master mode table 56. i2s slave mode timing (limited voltage range) num description min. max. unit operating voltage 2.7 3.6 v s11 i2s_bclk cycle time (input) 80 ns s12 i2s_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_fs input setup before i2s_bclk 4.5 ns s14 i2s_fs input hold after i2s_bclk 2 ns s15 i2s_bclk to i2s_txd/i2s_fs output valid 20 ns s16 i2s_bclk to i2s_txd/i2s_fs output invalid 0 ns s17 i2s_rxd setup before i2s_bclk 4.5 ns s18 i2s_rxd hold after i2s_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors 68 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_bclk (input) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd s19 figure 34. i 2 s timing slave modes 3.8.12.1 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 57. i2s/sai master mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk (as an input) pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 15 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 69 nxp semiconductors s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 35. i2s/sai timing master modes table 58. i2s/sai slave mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 80 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 4.5 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 23.1 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 4.5 ns s18 i2s_rxd hold after i2s_rx_bclk 2 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors 70 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 36. i2s/sai timing slave modes 3.8.12.2 vlpr, vlpw, and vlps mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 59. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 250 ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ns s7 i2s_tx_bclk to i2s_txd valid 45 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 45 ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ns peripheral operating requirements and behaviors kinetis k66 sub-family, rev. 4, 04/2017 71 nxp semiconductors s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd figure 37. i2s/sai timing master modes table 60. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s11 i2s_tx_bclk/i2s_rx_bclk cycle time (input) 250 ns s12 i2s_tx_bclk/i2s_rx_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_tx_fs/i2s_rx_fs input setup before i2s_tx_bclk/i2s_rx_bclk 30 ns s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 5 ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid 56.5 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ns s17 i2s_rxd setup before i2s_rx_bclk 30 ns s18 i2s_rxd hold after i2s_rx_bclk 5 ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear peripheral operating requirements and behaviors 72 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 figure 38. i2s/sai timing slave modes 3.9 human-machine interfaces (hmi) 3.9.1 tsi electrical specifications table 61. tsi electrical specifications symbol description min. typ. max. unit tsi_runf fixed power consumption in run mode 100 a tsi_runv variable power consumption in run mode (depends on oscillator's current selection) 1.0 128 a tsi_en power consumption in enable mode 100 a tsi_dis power consumption in disable mode 1.2 a tsi_ten tsi analog enable time 66 s tsi_cref tsi reference capacitor 1.0 pf tsi_dvolt voltage variation of vp & vm around nominal values 0.19 1.03 v 4 dimensions 4.1 obtaining package dimensions package dimensions are provided in package drawings. dimensions kinetis k66 sub-family, rev. 4, 04/2017 73 nxp semiconductors to find a package drawing, go to nxp.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 144-pin lqfp 98ass23177w 144-pin mapbga 98asa00222d 5 pinout 5.1 k66 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport l5 rtc_ wakeup_b rtc_ wakeup_b rtc_ wakeup_b m5 nc nc nc a10 nc nc nc b10 nc nc nc c10 nc nc nc 1 d3 pte0 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_tx sdhc0_d1 trace_ clkout i2c1_sda rtc_ clkout 2 d2 pte1/ llwu_p0 adc1_se5a adc1_se5a pte1/ llwu_p0 spi1_sout uart1_rx sdhc0_d0 trace_d3 i2c1_scl spi1_sin 3 d1 pte2/ llwu_p1 adc1_se6a adc1_se6a pte2/ llwu_p1 spi1_sck uart1_ cts_b sdhc0_ dclk trace_d2 4 e4 pte3 adc1_se7a adc1_se7a pte3 spi1_sin uart1_ rts_b sdhc0_ cmd trace_d1 spi1_sout 5 e5 vdd vdd vdd 6 h3 vss vss vss 7 e3 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_pcs0 uart3_tx sdhc0_d3 trace_d0 8 e2 pte5 disabled pte5 spi1_pcs2 uart3_rx sdhc0_d2 ftm3_ch0 9 e1 pte6/ llwu_p16 disabled pte6/ llwu_p16 spi1_pcs3 uart3_ cts_b i2s0_mclk ftm3_ch1 usb0_sof_ out 10 f4 pte7 disabled pte7 uart3_ rts_b i2s0_rxd0 ftm3_ch2 pinout 74 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 11 f3 pte8 disabled pte8 i2s0_rxd1 i2s0_rx_fs lpuart0_ tx ftm3_ch3 12 f2 pte9/ llwu_p17 disabled pte9/ llwu_p17 i2s0_txd1 i2s0_rx_ bclk lpuart0_ rx ftm3_ch4 13 f1 pte10/ llwu_p18 disabled pte10/ llwu_p18 i2c3_sda i2s0_txd0 lpuart0_ cts_b ftm3_ch5 usb1_id 14 g4 pte11 disabled pte11 i2c3_scl i2s0_tx_fs lpuart0_ rts_b ftm3_ch6 15 g3 pte12 disabled pte12 i2s0_tx_ bclk ftm3_ch7 16 e6 vdd vdd vdd 17 f7 vss vss vss 18 f6 vss vss vss 19 h1 usb0_dp usb0_dp usb0_dp 20 h2 usb0_dm usb0_dm usb0_dm 21 g1 vreg_out vreg_out vreg_out 22 g2 vreg_in0 vreg_in0 vreg_in0 23 j2 vreg_in1 disabled vreg_in1 24 k2 usb1_vss disabled usb1_vss 25 j1 usb1_dp disabled usb1_dp 26 k1 usb1_dm disabled usb1_dm 27 l1 usb1_vbus disabled usb1_vbus 28 l2 adc0_dm0/ adc1_dm3 adc0_dm0/ adc1_dm3 adc0_dm0/ adc1_dm3 29 m1 adc1_dp0/ adc0_dp3 adc1_dp0/ adc0_dp3 adc1_dp0/ adc0_dp3 30 m2 adc1_dm0/ adc0_dm3 adc1_dm0/ adc0_dm3 adc1_dm0/ adc0_dm3 31 h5 vdda vdda vdda 32 g5 vrefh vrefh vrefh 33 g6 vrefl vrefl vrefl 34 h6 vssa vssa vssa 35 k3 adc1_se16/ cmp2_in2/ adc0_se22 adc1_se16/ cmp2_in2/ adc0_se22 adc1_se16/ cmp2_in2/ adc0_se22 36 j3 adc0_se16/ cmp1_in2/ adc0_se21 adc0_se16/ cmp1_in2/ adc0_se21 adc0_se16/ cmp1_in2/ adc0_se21 37 m3 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 pinout kinetis k66 sub-family, rev. 4, 04/2017 75 nxp semiconductors 144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 38 l3 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 39 l4 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 40 m7 xtal32 xtal32 xtal32 41 m6 extal32 extal32 extal32 42 l6 vbat vbat vbat 43 vdd vdd vdd 44 vss vss vss 45 m4 pte24 adc0_se17 adc0_se17 pte24 can1_tx uart4_tx i2c0_scl ewm_out_ b 46 k5 pte25/ llwu_p21 adc0_se18 adc0_se18 pte25/ llwu_p21 can1_rx uart4_rx i2c0_sda ewm_in 47 k4 pte26 disabled pte26 enet_1588_ clkin uart4_ cts_b rtc_ clkout usb0_clkin 48 j4 pte27 disabled pte27 uart4_ rts_b 49 h4 pte28 disabled pte28 50 j5 pta0 jtag_tclk/ swd_clk/ ezp_clk tsi0_ch1 pta0 uart0_ cts_b/ uart0_ col_b ftm0_ch5 lpuart0_ cts_b jtag_tclk/ swd_clk ezp_clk 51 j6 pta1 jtag_tdi/ ezp_di tsi0_ch2 pta1 uart0_rx ftm0_ch6 i2c3_sda lpuart0_ rx jtag_tdi ezp_di 52 k6 pta2 jtag_tdo/ trace_ swo/ ezp_do tsi0_ch3 pta2 uart0_tx ftm0_ch7 i2c3_scl lpuart0_ tx jtag_tdo/ trace_ swo ezp_do 53 k7 pta3 jtag_tms/ swd_dio tsi0_ch4 pta3 uart0_ rts_b ftm0_ch0 lpuart0_ rts_b jtag_tms/ swd_dio 54 l7 pta4/ llwu_p3 nmi_b/ ezp_cs_b tsi0_ch5 pta4/ llwu_p3 ftm0_ch1 nmi_b ezp_cs_b 55 m8 pta5 disabled pta5 usb0_clkin ftm0_ch2 rmii0_ rxer/ mii0_rxer cmp2_out i2s0_tx_ bclk jtag_ trst_b 56 e7 vdd vdd vdd 57 g7 vss vss vss 58 j7 pta6 disabled pta6 ftm0_ch3 clkout trace_ clkout 59 j8 pta7 adc0_se10 adc0_se10 pta7 ftm0_ch4 rmii0_mdio/ mii0_mdio trace_d3 pinout 76 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 60 k8 pta8 adc0_se11 adc0_se11 pta8 ftm1_ch0 rmii0_mdc/ mii0_mdc ftm1_qd_ pha/ tpm1_ch0 trace_d2 61 l8 pta9 disabled pta9 ftm1_ch1 mii0_rxd3 ftm1_qd_ phb/ tpm1_ch1 trace_d1 62 m9 pta10/ llwu_p22 disabled pta10/ llwu_p22 ftm2_ch0 mii0_rxd2 ftm2_qd_ pha/ tpm2_ch0 trace_d0 63 l9 pta11/ llwu_p23 disabled pta11/ llwu_p23 ftm2_ch1 mii0_rxclk i2c2_sda ftm2_qd_ phb/ tpm2_ch1 64 k9 pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 rmii0_ rxd1/ mii0_rxd1 i2c2_scl i2s0_txd0 ftm1_qd_ pha/ tpm1_ch0 65 j9 pta13/ llwu_p4 cmp2_in1 cmp2_in1 pta13/ llwu_p4 can0_rx ftm1_ch1 rmii0_ rxd0/ mii0_rxd0 i2c2_sda i2s0_tx_fs ftm1_qd_ phb/ tpm1_ch1 66 l10 pta14 disabled pta14 spi0_pcs0 uart0_tx rmii0_crs_ dv/ mii0_rxdv i2c2_scl i2s0_rx_ bclk i2s0_txd1 67 l11 pta15 cmp3_in1 cmp3_in1 pta15 spi0_sck uart0_rx rmii0_ txen/ mii0_txen i2s0_rxd0 68 k10 pta16 cmp3_in2 cmp3_in2 pta16 spi0_sout uart0_ cts_b/ uart0_ col_b rmii0_txd0/ mii0_txd0 i2s0_rx_fs i2s0_rxd1 69 k11 pta17 adc1_se17 adc1_se17 pta17 spi0_sin uart0_ rts_b rmii0_txd1/ mii0_txd1 i2s0_mclk 70 e8 vdd vdd vdd 71 g8 vss vss vss 72 m12 pta18 extal0 extal0 pta18 ftm0_flt2 ftm_clkin0 tpm_ clkin0 73 m11 pta19 xtal0 xtal0 pta19 ftm1_flt0 ftm_clkin1 lptmr0_ alt1 tpm_ clkin1 74 l12 reset_b reset_b reset_b 75 k12 pta24 cmp3_in4 cmp3_in4 pta24 mii0_txd2 fb_a29 76 j12 pta25 cmp3_in5 cmp3_in5 pta25 mii0_txclk fb_a28 77 j11 pta26 disabled pta26 mii0_txd3 fb_a27 78 j10 pta27 disabled pta27 mii0_crs fb_a26 79 h12 pta28 disabled pta28 mii0_txer fb_a25 80 h11 pta29 disabled pta29 mii0_col fb_a24 81 h10 ptb0/ llwu_p5 adc0_se8/ adc1_se8/ tsi0_ch0 adc0_se8/ adc1_se8/ tsi0_ch0 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 rmii0_mdio/ mii0_mdio sdram_ cas_b ftm1_qd_ pha/ tpm1_ch0 pinout kinetis k66 sub-family, rev. 4, 04/2017 77 nxp semiconductors 144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 82 h9 ptb1 adc0_se9/ adc1_se9/ tsi0_ch6 adc0_se9/ adc1_se9/ tsi0_ch6 ptb1 i2c0_sda ftm1_ch1 rmii0_mdc/ mii0_mdc sdram_ ras_b ftm1_qd_ phb/ tpm1_ch1 83 g12 ptb2 adc0_se12/ tsi0_ch7 adc0_se12/ tsi0_ch7 ptb2 i2c0_scl uart0_ rts_b enet0_ 1588_tmr0 sdram_we ftm0_flt3 84 g11 ptb3 adc0_se13/ tsi0_ch8 adc0_se13/ tsi0_ch8 ptb3 i2c0_sda uart0_ cts_b/ uart0_ col_b enet0_ 1588_tmr1 sdram_ cs0_b ftm0_flt0 85 g10 ptb4 adc1_se10 adc1_se10 ptb4 enet0_ 1588_tmr2 sdram_ cs1_b ftm1_flt0 86 g9 ptb5 adc1_se11 adc1_se11 ptb5 enet0_ 1588_tmr3 ftm2_flt0 87 f12 ptb6 adc1_se12 adc1_se12 ptb6 fb_ad23/ sdram_d23 88 f11 ptb7 adc1_se13 adc1_se13 ptb7 fb_ad22/ sdram_d22 89 f10 ptb8 disabled ptb8 uart3_ rts_b fb_ad21/ sdram_d21 90 f9 ptb9 disabled ptb9 spi1_pcs1 uart3_ cts_b fb_ad20/ sdram_d20 91 e12 ptb10 adc1_se14 adc1_se14 ptb10 spi1_pcs0 uart3_rx fb_ad19/ sdram_d19 ftm0_flt1 92 e11 ptb11 adc1_se15 adc1_se15 ptb11 spi1_sck uart3_tx fb_ad18/ sdram_d18 ftm0_flt2 93 h7 vss vss vss 94 f5 vdd vdd vdd 95 e10 ptb16 tsi0_ch9 tsi0_ch9 ptb16 spi1_sout uart0_rx ftm_clkin0 fb_ad17/ sdram_d17 ewm_in tpm_ clkin0 96 e9 ptb17 tsi0_ch10 tsi0_ch10 ptb17 spi1_sin uart0_tx ftm_clkin1 fb_ad16/ sdram_d16 ewm_out_ b tpm_ clkin1 97 d12 ptb18 tsi0_ch11 tsi0_ch11 ptb18 can0_tx ftm2_ch0 i2s0_tx_ bclk fb_ad15/ sdram_a23 ftm2_qd_ pha/ tpm2_ch0 98 d11 ptb19 tsi0_ch12 tsi0_ch12 ptb19 can0_rx ftm2_ch1 i2s0_tx_fs fb_oe_b ftm2_qd_ phb/ tpm2_ch1 99 d10 ptb20 disabled ptb20 spi2_pcs0 fb_ad31/ sdram_d31 cmp0_out 100 d9 ptb21 disabled ptb21 spi2_sck fb_ad30/ sdram_d30 cmp1_out 101 c12 ptb22 disabled ptb22 spi2_sout fb_ad29/ sdram_d29 cmp2_out 102 c11 ptb23 disabled ptb23 spi2_sin spi0_pcs5 fb_ad28/ sdram_d28 cmp3_out pinout 78 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 103 b12 ptc0 adc0_se14/ tsi0_ch13 adc0_se14/ tsi0_ch13 ptc0 spi0_pcs4 pdb0_ extrg usb0_sof_ out fb_ad14/ sdram_a22 i2s0_txd1 104 b11 ptc1/ llwu_p6 adc0_se15/ tsi0_ch14 adc0_se15/ tsi0_ch14 ptc1/ llwu_p6 spi0_pcs3 uart1_ rts_b ftm0_ch0 fb_ad13/ sdram_a21 i2s0_txd0 105 a12 ptc2 adc0_se4b/ cmp1_in0/ tsi0_ch15 adc0_se4b/ cmp1_in0/ tsi0_ch15 ptc2 spi0_pcs2 uart1_ cts_b ftm0_ch1 fb_ad12/ sdram_a20 i2s0_tx_fs 106 a11 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 clkout i2s0_tx_ bclk 107 h8 vss vss vss 108 vdd vdd vdd 109 a9 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 fb_ad11/ sdram_a19 cmp1_out 110 d8 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 i2s0_rxd0 fb_ad10/ sdram_a18 cmp0_out ftm0_ch2 111 c8 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_ extrg i2s0_rx_ bclk fb_ad9/ sdram_a17 i2s0_mclk 112 b8 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin usb0_sof_ out i2s0_rx_fs fb_ad8/ sdram_a16 113 a8 ptc8 adc1_se4b/ cmp0_in2 adc1_se4b/ cmp0_in2 ptc8 ftm3_ch4 i2s0_mclk fb_ad7/ sdram_a15 114 d7 ptc9 adc1_se5b/ cmp0_in3 adc1_se5b/ cmp0_in3 ptc9 ftm3_ch5 i2s0_rx_ bclk fb_ad6/ sdram_a14 ftm2_flt0 115 c7 ptc10 adc1_se6b adc1_se6b ptc10 i2c1_scl ftm3_ch6 i2s0_rx_fs fb_ad5/ sdram_a13 116 b7 ptc11/ llwu_p11 adc1_se7b adc1_se7b ptc11/ llwu_p11 i2c1_sda ftm3_ch7 i2s0_rxd1 fb_rw_b 117 a7 ptc12 disabled ptc12 uart4_ rts_b ftm_clkin0 fb_ad27/ sdram_d27 ftm3_flt0 tpm_ clkin0 118 d6 ptc13 disabled ptc13 uart4_ cts_b ftm_clkin1 fb_ad26/ sdram_d26 tpm_ clkin1 119 c6 ptc14 disabled ptc14 uart4_rx fb_ad25/ sdram_d25 120 b6 ptc15 disabled ptc15 uart4_tx fb_ad24/ sdram_d24 121 vss vss vss 122 vdd vdd vdd 123 a6 ptc16 disabled ptc16 can1_rx uart3_rx enet0_ 1588_tmr0 fb_cs5_b/ fb_tsiz1/ fb_be23_ 16_bls15_ 8_b/ sdram_ dqm2 124 d5 ptc17 disabled ptc17 can1_tx uart3_tx enet0_ 1588_tmr1 fb_cs4_b/ fb_tsiz0/ pinout kinetis k66 sub-family, rev. 4, 04/2017 79 nxp semiconductors 144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport fb_be31_ 24_bls7_0_ b/ sdram_ dqm3 125 c5 ptc18 disabled ptc18 uart3_ rts_b enet0_ 1588_tmr2 fb_tbst_b/ fb_cs2_b/ fb_be15_8_ bls23_16_b/ sdram_ dqm1 126 b5 ptc19 disabled ptc19 uart3_ cts_b enet0_ 1588_tmr3 fb_cs3_b/ fb_be7_0_ bls31_24_b/ sdram_ dqm0 fb_ta_b 127 a5 ptd0/ llwu_p12 disabled ptd0/ llwu_p12 spi0_pcs0 uart2_ rts_b ftm3_ch0 fb_ale/ fb_cs1_b/ fb_ts_b 128 d4 ptd1 adc0_se5b adc0_se5b ptd1 spi0_sck uart2_ cts_b ftm3_ch1 fb_cs0_b 129 c4 ptd2/ llwu_p13 disabled ptd2/ llwu_p13 spi0_sout uart2_rx ftm3_ch2 fb_ad4/ sdram_a12 i2c0_scl 130 b4 ptd3 disabled ptd3 spi0_sin uart2_tx ftm3_ch3 fb_ad3/ sdram_a11 i2c0_sda 131 a4 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi0_pcs1 uart0_ rts_b ftm0_ch4 fb_ad2/ sdram_a10 ewm_in spi1_pcs0 132 a3 ptd5 adc0_se6b adc0_se6b ptd5 spi0_pcs2 uart0_ cts_b/ uart0_ col_b ftm0_ch5 fb_ad1/ sdram_a9 ewm_out_ b spi1_sck 133 a2 ptd6/ llwu_p15 adc0_se7b adc0_se7b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 fb_ad0 ftm0_flt0 spi1_sout 134 m10 vss vss vss 135 f8 vdd vdd vdd 136 a1 ptd7 disabled ptd7 cmt_iro uart0_tx ftm0_ch7 sdram_ cke ftm0_flt1 spi1_sin 137 c9 ptd8/ llwu_p24 disabled ptd8/ llwu_p24 i2c0_scl lpuart0_ rx fb_a16 138 b9 ptd9 disabled ptd9 i2c0_sda lpuart0_ tx fb_a17 139 b3 ptd10 disabled ptd10 lpuart0_ rts_b fb_a18 140 b2 ptd11/ llwu_p25 disabled ptd11/ llwu_p25 spi2_pcs0 sdhc0_ clkin lpuart0_ cts_b fb_a19 141 b1 ptd12 disabled ptd12 spi2_sck ftm3_flt0 sdhc0_d4 fb_a20 142 c3 ptd13 disabled ptd13 spi2_sout sdhc0_d5 fb_a21 pinout 80 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 144 lqfp 144 map bga pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport 143 c2 ptd14 disabled ptd14 spi2_sin sdhc0_d6 fb_a22 144 c1 ptd15 disabled ptd15 spi2_pcs1 sdhc0_d7 fb_a23 5.2 recommended connection for unused analog and digital pins table 62 shows the recommended connections for analog interface pins if those analog interfaces are not used in the customer's application table 62. recommended connection for unused analog interfaces pin type k66 short recommendation detailed recommendation analog/non gpio adcx/cmpx float analog input - float analog/non gpio vref_out float analog output - float analog/non gpio dac0_out, dac1_out float analog output - float analog/non gpio rtc_wakeup_b float analog output - float analog/non gpio xtal32 float analog output - float analog/non gpio extal32 float analog input - float gpio/analog pta18/extal0 float analog input - float gpio/analog pta19/xtal0 float analog output - float gpio/analog ptx/adcx float float (default is analog input) gpio/analog ptx/cmpx float float (default is analog input) gpio/analog ptx/tsiox float float (default is analog input) gpio/digital pta0/jtag_tclk float float (default is jtag with pulldown) gpio/digital pta1/jtag_tdi float float (default is jtag with pullup) gpio/digital pta2/jtag_tdo float float (default is jtag with pullup) gpio/digital pta3/jtag_tms float float (default is jtag with pullup) gpio/digital pta4/nmi_b 10k? pullup or disable and float pull high or disable in pcr & fopt and float gpio/digital ptx float float (default is disabled) usb usb0_dp float float usb usb0_dm float float usb vreg_out tie to input and ground through 10k? tie to input and ground through 10k? usb vreg_in0 tie to output and ground through 10k? tie to output and ground through 10k? table continues on the next page... pinout kinetis k66 sub-family, rev. 4, 04/2017 81 nxp semiconductors table 62. recommended connection for unused analog interfaces (continued) pin type k66 short recommendation detailed recommendation usb vreg_in1 tie to output and ground through 10k? tie to output and ground through 10k? usb usb1_vss always connect to vss always connect to vss usb usb1_dp float float usb usb1_dm float float usb usb1_vbus float float vbat vbat float float vdda vdda always connect to vdd potential always connect to vdd potential vrefh vrefh always connect to vdd potential always connect to vdd potential vrefl vrefl always connect to vss potential always connect to vss potential vssa vssa always connect to vss potential always connect to vss potential 5.3 k66 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout 82 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 75 74 73 60 59 58 57 56 55 54 53 52 51 72 71 70 69 68 67 66 65 64 63 62 61 25 24 23 22 21 40 39 38 37 50 49 48 47 46 45 44 43 42 41 36 35 34 33 32 31 30 29 28 27 26 99 79 78 77 76 98 97 96 95 94 93 92 91 90 89 88 80 81 82 83 84 85 86 87 100 108 vdd 107 106 105 104 103 102 101 vss ptc3/llwu_p7 ptc2 ptc1/llwu_p6 ptc0 ptb23 ptb22 116 ptc11/llwu_p11 115 114 113 112 111 110 109 ptc10 ptc9 ptc8 ptc7 ptc6/llwu_p10 ptc5/llwu_p9 ptc4/llwu_p8 124 ptc17 123 122 121 120 119 118 117 ptc16 vdd vss ptc15 ptc14 ptc13 ptc12 132 ptd5 131 130 129 128 127 126 125 ptd4/llwu_p14 ptd3 ptd2/llwu_p13 ptd1 ptd0/llwu_p12 ptc19 ptc18 140 ptd11/llwu_p25 139 138 137 136 135 134 133 ptd10 ptd9 ptd8/llwu_p24 ptd7 vdd vss ptd6/llwu_p15 144 143 142 141 ptd15 ptd14 ptd13 ptd12 ptb20 pta28 pta27 pta26 pta25 ptb19 ptb18 ptb17 ptb16 vdd vss ptb11 ptb10 ptb9 ptb8 ptb7 pta29 ptb0/llwu_p5 ptb1 ptb2 ptb3 ptb4 ptb5 ptb6 ptb21 pta24 reset_b pta19 pta18 vss vdd pta17 pta16 pta15 pta14 pta13/llwu_p4 pta12 pta11/llwu_p23 pta10/llwu_p22 pta9 pta8 pta7 pta6 vss vdd pta5 pta4/llwu_p3 pta3 pta2 pta1 pta0 pte28 pte27 pte26 pte25/llwu_p21 pte24 vss vdd vbat extal32 xtal32 dac1_out/cmp0_in4/cmp2_in3/adc1_se23 dac0_out/cmp1_in3/adc0_se23 vref_out/cmp1_in5/cmp0_in5/adc1_se18 usb0_dm usb0_dp vss vss vdd pte12 pte11 pte10/llwu_p18 pte9/llwu_p17 pte8 pte7 pte6/llwu_p16 pte5 pte4/llwu_p2 vss vdd pte3 pte2/llwu_p1 pte1/llwu_p0 pte0 usb1_dp usb1_vss vreg_in1 vreg_in0 vreg_out adc0_se16/cmp1_in2/adc0_se21 adc1_se16/cmp2_in2/adc0_se22 vssa vrefl vrefh vdda adc1_dm0/adc0_dm3 adc1_dp0/adc0_dp3 adc0_dm0/adc1_dm3 usb1_vbus usb1_dm figure 39. k66 144 lqfp pinout diagram pinout kinetis k66 sub-family, rev. 4, 04/2017 83 nxp semiconductors 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 a b c d e f g h j a b c d e f g h j 10 k k 10 11 11 l l 12 12 m m pta18 ptc8 ptc4/ llwu_p8 nc ptc3/ llwu_p7 ptc2 pta1 pta6pta0pte27 adc0_se16/ cmp1_in2/ adc0_se21 adc1_se16/ cmp2_in2/ adc0_se22 pte26 pte25/ llwu_p21 pta2 pta3 pta8 pta7 vssvssvssavddapte28vssusb0_dm vreg_in1 usb1_vss adc0_dm0/ adc1_dm3 dac0_out/ cmp1_in3/ adc0_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 rtc_ wakeup_b vbat pta4/ llwu_p3 pta9 pta11/ llwu_p23 pta12 pta13/ llwu_p4 ptb1 pta27 ptb0/ llwu_p5 ptb4ptb5vssvssvreflvrefhpte11pte12vreg_in0vreg_out usb0_dp usb1_dp usb1_dm usb1_vbus adc1_dp0/ adc0_dp3 adc1_dm0/ adc0_dm3 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 pte24 nc extal32 xtal32 pta5 pta10/ llwu_p22 vss pta16 pta14 ptb3 pta29 pta26 pta17 pta15 pta19 reset_b pta24 pta25 pta28 ptb2 ptb6ptb7ptb8ptb9vdd vdd ptb17 ptb16 ptb10ptb11 ptb19 ptb18 ptb22ptb23nc ptb20ptb21ptc5/ llwu_p9 ptd8/ llwu_p24 ptc6/ llwu_p10 ptc7 ptd9 nc ptc1/ llwu_p6 ptc0 vss vss vddvdd ptc13 ptc9 ptc11/ llwu_p11 ptc10 ptc19 ptc15 ptc14ptc18ptd2/ llwu_p13 ptd3ptd10 ptd13 pte0 ptd1 ptc17 vdd vddpte7 pte3pte4/ llwu_p2 pte8pte9/ llwu_p17 pte10/ llwu_p18 pte6/ llwu_p16 pte5 pte1/ llwu_p0 pte2/ llwu_p1 ptd15 ptd14 ptd11/ llwu_p25 ptd12 ptc12ptc16ptd0/ llwu_p12 ptd4/ llwu_p14 ptd5 ptd6/ llwu_p15 ptd7 figure 40. k66 144 mapbga pinout diagram 6 ordering parts ordering parts 84 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 6.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: pk66 and mk66 7 part identification 7.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 7.2 format part numbers for this device have the following format: q k## a m fff r t pp cc n 7.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow ? p = prequalification k## kinetis family ? k65 ? k66 a key attribute ? d = cortex-m4 w/ dsp ? f = cortex-m4 w/ dsp and fpu m flash memory type ? n = program flash only ? x = program flash and flexmemory fff program flash memory size ? 32 = 32 kb ? 64 = 64 kb ? 128 = 128 kb ? 256 = 256 kb ? 512 = 512 kb ? 768 = 768 kb table continues on the next page... part identification kinetis k66 sub-family, rev. 4, 04/2017 85 nxp semiconductors field description values ? 1m0 = 1 mb ? 2m0 = 2 mb r silicon revision ? z = initial ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 ? c = C40 to 85 pp package identifier ? fm = 32 qfn (5 mm x 5 mm) ? ft = 48 qfn (7 mm x 7 mm) ? lf = 48 lqfp (7 mm x 7 mm) ? lh = 64 lqfp (10 mm x 10 mm) ? mp = 64 mapbga (5 mm x 5 mm) ? lk = 80 lqfp (12 mm x 12 mm) ? ll = 100 lqfp (14 mm x 14 mm) ? mc = 121 mapbga (8 mm x 8 mm) ? lq = 144 lqfp (20 mm x 20 mm) ? md = 144 mapbga (13 mm x 13 mm) ? mi= 169 mapbga (9 mm x 9 mm) ? ac= 169 wlcsp (5.6 mm x 5.5 mm) cc maximum cpu frequency (mhz) ? 5 = 50 mhz ? 7 = 72 mhz ? 10 = 100 mhz ? 12 = 120 mhz ? 15 = 150 mhz ? 16 = 168 mhz ? 18 = 180 mhz n packaging type ? r = tape and reel ? (blank) = trays 7.4 example this is an example part number: mk66fn2m0vmd18 8 terminology and guidelines 8.1 definitions key terms are defined in the following table: terminology and guidelines 86 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors term definition rating a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. note: the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. operating requirement a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip operating behavior a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions typical value a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions note: typical values are provided as design guidelines and are neither tested nor guaranteed. 8.2 examples operating rating : operating requirement : operating behavior that includes a typical value : example example example example terminology and guidelines kinetis k66 sub-family, rev. 4, 04/2017 87 nxp semiconductors 8.3 typical-value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd supply voltage 3.3 v 8.4 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 8.5 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. terminology and guidelines 88 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors 9 revision history the following table provides a revision history for this document. table 63. revision history rev. no. date substantial changes 0 02/2015 initial release 1 04/2015 ? editorial change ? updated otg/eh and bc rev. 1.2 specification references in usb full speed transceiver and high speed phy specifications section ? updated usbdcd electrical specifications table ? updated the typical values and maximum values of specs in power consumption operating behaviors table ? removed pstop2 current from power consumption operating behaviors table ? updated the values of ds5 and ds7 in master mode dspi timing (full voltage range) table ? updated the footnote and description of v dio , v aio and i d in voltage and current operating ratings table ? updated the values and description of specs in voltage and current operating requirements table ? updated the leakage current specs in voltage and current operating behaviors table ? added notes column in thermal operating requirements ? updated the values of 48mhz irc in low power mode peripheral adders table ? added new footnotes for i inrush in usb vreg electrical specifications table to better document operation. ? updated the figures "sdram write timing diagram" and sdram read timing diagram" in the section "sdram controller specifications." ? updated the pinout table, and pinout diagrams in the section "pinouts." 2 05/2015 ? added new footnotes for i inrush in usb vreg electrical specifications table to better document operation. ? updated the figures "sdram write timing diagram" and sdram read timing diagram" in the section "sdram controller specifications." ? updated the pinout table, and pinout diagrams in the section "pinouts." 3 01/2016 ? updated the symbol in footnote of thermal operating specs ? updated the description of pll operating current in mcg specifications table ? updated the values of irc48m specifications table ? added usb fs and usb hs logo in front page ? updated terminology and guidelines section ? updated the maximum values of i dd_lls2 and i dd_lls3 in power consumption operating behaviors table 4 03/2017 ? removed the verbiage of "except rtc_wakeup pins" from the description for r pu and r pd in voltage and current operating behaviors table ? updated the unit of adc conversion rate from "kbps" to "ks/s" in 16-bit adc operating conditions table ? added mii signal switching specifications table and rmii signal switching specifications table for full voltage range ? added mdio serial management timing specifications section ? updated i2c switching specifications section ? updated the minimum and maximum value of voltage reference output with factory trim in vref full-range operating requirements table in voltage reference electrical specifications section revision history kinetis k66 sub-family, rev. 4, 04/2017 89 nxp semiconductors revision history 90 kinetis k66 sub-family, rev. 4, 04/2017 nxp semiconductors how to reach us: home page: nxp.com web support: nxp.com/support information in this document is provided solely to enable system and software implementers to use nxp products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions . nxp, the nxp logo, nxp secure connections for a smarter world, freescale, the freescale logo, and kinetis are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm, the arm powered logo, and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. the usb-if logo is a registered trademark of usb implementers forum, inc. all rights reserved. ? 2013C2017 nxp b.v. document number K66P144M180SF5V2 revision 4, 04/2017 |
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